Symbolic Reasoning — Spike-Based Logic¶
Turing-complete symbolic computation using only spiking neurons. LIF neurons configured as logic gates compose into half-adder, full-adder, ALU, comparator, and sorting network.
Architecture¶
Each gate maps to a specific LIF configuration:
| Gate | LIF Threshold | Weights | Behavior |
|---|---|---|---|
| AND | 2 | [1, 1] | Both inputs must fire |
| OR | 1 | [1, 1] | Either input fires |
| NOT | 0 | [-1] | Inhibitory inversion |
| NAND | 0 | [-1, -1], bias=2 | AND + NOT |
| XOR | 1 | [1, 1], inhibit_if_both | Odd-parity |
The SpikeALU composes these gates into a ripple-carry adder for N-bit integer arithmetic. Addition: sum = a XOR b XOR carry, carry = (a AND b) OR (carry AND (a XOR b)). Subtraction via two's complement.
Components¶
SpikeGate— Configurable spike logic gate. Supports AND, OR, NOT, NAND, XOR. Thelif_configproperty returns LIF neuron parameters that reproduce the gate behavior in simulation.SpikeRegister— N-bit register using SR latch pairs (mutual inhibition). Read/write integer values or raw bit arrays.SpikeALU— N-bit Arithmetic Logic Unit. Operations:add,sub,bitwise_and,bitwise_or,bitwise_xor,compare,shift_left,shift_right.spike_sort— Sort integers using a bubble-sort comparison network built from SpikeALU.compare.
Usage¶
from sc_neurocore.symbolic import SpikeGate, SpikeRegister, SpikeALU, spike_sort
# Logic gates
xor = SpikeGate("XOR")
assert xor(1, 0) == 1
# 8-bit ALU
alu = SpikeALU(8)
result, carry = alu.add(100, 50) # 150, False
result, carry = alu.add(200, 100) # 44, True (overflow)
# 16-bit ALU for larger values
alu16 = SpikeALU(16)
result, _ = alu16.add(30000, 30000) # 60000
# Spike-based sorting
sorted_vals = spike_sort([3, 1, 4, 1, 5, 9, 2, 6])
Reference: Plana et al. 2022 — Spike-based logic gates on SpiNNaker.
See Tutorial 71: Symbolic Reasoning.
sc_neurocore.symbolic
¶
Spike-based logic gates, registers, ALU. Turing-complete spike computation.
SpikeGate
dataclass
¶
Spike-based logic gate.
Parameters¶
gate_type : str 'AND', 'OR', 'NOT', 'NAND', 'XOR'
Source code in src/sc_neurocore/symbolic/spike_logic.py
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lif_config
property
¶
LIF neuron configuration for this gate.
Returns threshold, excitatory/inhibitory input weights.
SpikeRegister
¶
Spike-based register: stores N bits using SR latch pairs.
Each bit is held by two neurons in mutual inhibition (bistable). Write: inject spike to set/reset neuron. Read: check which neuron of each pair is active.
Parameters¶
n_bits : int Register width.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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write(value)
¶
Write an integer value to the register.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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read()
¶
Read the register as an integer.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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write_bits(bits)
¶
Write raw bit array.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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read_bits()
¶
Read raw bit array.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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SpikeALU
¶
Spike-based Arithmetic Logic Unit.
Operations: ADD, SUB, AND, OR, XOR, CMP, SHIFT_LEFT, SHIFT_RIGHT. All implemented via spike-gate compositions.
Parameters¶
n_bits : int Word width.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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add(a, b)
¶
Ripple-carry addition. Returns (result, carry_out).
Source code in src/sc_neurocore/symbolic/spike_logic.py
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sub(a, b)
¶
Subtraction via two's complement: a - b = a + (~b + 1).
Source code in src/sc_neurocore/symbolic/spike_logic.py
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compare(a, b)
¶
Compare: returns -1, 0, or 1.
Source code in src/sc_neurocore/symbolic/spike_logic.py
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spike_sort(values, n_bits=8)
¶
Sort integers using spike-based comparison network.
Uses a bubble-sort topology where each compare-and-swap is implemented via SpikeALU.compare.
Parameters¶
values : list of int n_bits : int
Returns¶
list of int, sorted ascending
Source code in src/sc_neurocore/symbolic/spike_logic.py
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