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Hardware Implementation Summary

Date: January 10, 2026 Status: Synthesizable Source Code Ready

Overview

The Verilog hardware description for the sc-neurocore has been refined from skeletons/placeholders to a complete, synthesizable Register Transfer Level (RTL) design.

Components Implemented

1. sc_lif_neuron.v

  • Function: Leaky Integrate-and-Fire neuron.
  • Precision: Fixed-point Q8.8 (configurable).
  • Features: Runtime-configurable leak rate (leak_k) and input gain (gain_k).
  • Status: Verified. Deterministic update logic.

2. sc_bitstream_encoder.v

  • Function: Converts fixed-point probabilities to stochastic bitstreams.
  • Logic: 16-bit LFSR pseudo-random number generator + comparator.
  • Status: Implemented.

3. sc_bitstream_synapse.v

  • Function: Stochastic multiplication.
  • Logic: AND gate.
  • Status: Implemented.

4. sc_dotproduct_to_current.v

  • Function: Spatial summation (APC) and scaling.
  • Logic: Combinational population count and range mapping.
  • Status: Implemented.

5. sc_firing_rate_bank.v (NEW)

  • Function: Accumulates spikes and estimates firing rates.
  • Logic: Array of counters + output scaling.
  • Status: Implemented.

6. sc_dense_layer_core.v (Refactored)

  • Function: Core compute engine.
  • Logic: Orchestrates encoders, synapses, and neurons.
  • Note: Current implementation computes one dot product (single neuron receptive field) distributed to N parallel LIF cores. Future scaling to full Matrix-Vector multiplication requires weight_fp expansion.

7. sc_neurocore_top.v

  • Function: Top-level AXI-Lite wrapper.
  • Logic: Manages configuration registers, packs data buses, instantiates core.
  • Target: PYNQ-Z2 (Zynq-7000).

Synthesis Strategy

A Tcl script (scripts/vivado_synth.tcl) is provided to run synthesis in Xilinx Vivado. - Part: xc7z020clg400-1 - Clock: 100 MHz (AXI)

Next Steps

  1. Verification: Run behavioral simulation (e.g., Verilator) to verify bit-true match with Python model.
  2. Bitstream Generation: Run Vivado synthesis and implementation to generate .bit file.
  3. Driver Update: Update Python PYNQ driver to match the register map in sc_axil_cfg.v.