sc_neurocore_engine/ir/mod.rs
1// SPDX-License-Identifier: AGPL-3.0-or-later
2// Commercial license available
3// © Concepts 1996–2026 Miroslav Šotek. All rights reserved.
4// © Code 2020–2026 Miroslav Šotek. All rights reserved.
5// ORCID: 0009-0009-3560-0851
6// Contact: www.anulum.li | protoscience@anulum.li
7// SC-NeuroCore — SC Compute Graph IR
8
9//! # SC Compute Graph IR
10//!
11//! A Rust-native intermediate representation for stochastic computing
12//! pipelines. The IR captures the semantics of the planned MLIR "sc"
13//! dialect (Blueprint §5) and can be lowered directly to synthesizable
14//! SystemVerilog or exported as a text format for future MLIR/CIRCT
15//! integration.
16//!
17//! # Design Principles
18//!
19//! - **SSA**: Every operation produces exactly one named value.
20//! - **Typed**: All values carry an `ScType` for static verification.
21//! - **Acyclic**: The operation list forms a DAG (verified by `verify()`).
22//! - **Portable**: No external dependencies; pure Rust enums and structs.
23
24pub mod builder;
25pub mod emit_mlir;
26pub mod emit_sv;
27pub mod graph;
28pub mod parser;
29pub mod printer;
30pub mod verify;