sc_neurocore_engine/ir/mod.rs
1// SPDX-License-Identifier: AGPL-3.0-or-later | Commercial license available
2// © Concepts 1996–2026 Miroslav Šotek. All rights reserved.
3// © Code 2020–2026 Miroslav Šotek. All rights reserved.
4// ORCID: 0009-0009-3560-0851
5// Contact: www.anulum.li | protoscience@anulum.li
6// SC-NeuroCore — SC Compute Graph IR
7
8//! # SC Compute Graph IR
9//!
10//! A Rust-native intermediate representation for stochastic computing
11//! pipelines. The IR captures the semantics of the planned MLIR "sc"
12//! dialect (Blueprint §5) and can be lowered directly to synthesizable
13//! SystemVerilog or exported as a text format for future MLIR/CIRCT
14//! integration.
15//!
16//! # Design Principles
17//!
18//! - **SSA**: Every operation produces exactly one named value.
19//! - **Typed**: All values carry an `ScType` for static verification.
20//! - **Acyclic**: The operation list forms a DAG (verified by `verify()`).
21//! - **Portable**: No external dependencies; pure Rust enums and structs.
22
23pub mod builder;
24pub mod emit_mlir;
25pub mod emit_sv;
26pub mod graph;
27pub mod parser;
28pub mod printer;
29pub mod verify;