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Loop Timing Witness
Native controller and runtime interfaces; hardware qualification pending
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#include <simulation.h>
Public Member Functions | |
| Simulation () | |
| ~Simulation () | |
| std::uint64_t | time () const |
| void | advance (std::uint64_t nanoseconds) |
| Edge | read (std::uint8_t address) |
| Edge | write (std::uint8_t address, std::uint32_t data, std::uint8_t strobes) |
| bool | wait_interrupt (std::uint64_t nanoseconds) |
Deterministic 7 ns bus and 5 ns capture half-periods, with real CDC logic.
Definition at line 34 of file simulation.h.
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Assert the external common reset and release both actual clock domains.
Definition at line 65 of file simulation.h.
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Finalize the model before freeing the Verilator context.
Definition at line 74 of file simulation.h.
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Advance both clocks while the native process has requested idle time.
Definition at line 80 of file simulation.h.
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Read through AR/R channels; return the actual destination AXI response.
Definition at line 86 of file simulation.h.
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Return nanoseconds elapsed in this simulation, never host wall time.
Definition at line 77 of file simulation.h.
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Advance up to a bounded wait, returning the retained bus-domain IRQ level.
Definition at line 125 of file simulation.h.
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Submit independent AW/W channels, then retain the actual B response.
Definition at line 103 of file simulation.h.