ADR 0001 — Repository boundary and ownership

Status: accepted, 2026-09-15

Decider: project owner, Miroslav Šotek

Context

SC-NeuroCore, an open neuromorphic computing library, integrates generated neuron peripherals into RISC-V systems-on-chip, including PolarFire SoC, and documents a latency budget for the memory-mapped path between processor and fabric. That budget is an estimate: no board measurement of it exists, and physical board validation is an open item of the library's roadmap. More generally, real-time control on systems-on-chip is usually timed by software on the processor under test, and published fabric-based measurements address single interrupt pairs rather than complete control loops across placements.

On 2026-09-14 the owner decided to build a separate measurement instrument as its own repository in the SC Neuromorphic Computing Systems portfolio group, independent of any single application, and on 2026-09-15 approved the name LOOP-TIMING-WITNESS.

Decision

1. The repository owns the measurement instrument: fabric timebase and event witness, plant emulator, deadline and safe-state monitor, fault injector, textbook fabric controllers, processor-subsystem software for the three placements, the Linux run controller and power logger, the host analysis tool, the run manifest format, the measurement protocol and the scripts that generate vendor tool projects.
2. The repository contains no SC-NeuroCore source code, generated peripheral, model or adapter. Adapters that place an accelerator library's peripherals in the device-under-test slot live in that library's repository and consume this repository's published manifest format and slot interface.
3. Controllers are textbook PID with anti-windup and discrete LQR only. Controllers, plant models and physics from other projects are out of scope.
4. Vendor tools, licensed or encrypted IP cores and vendor reference designs are never committed; projects are generated by scripts and vendor software is fetched at pinned revisions.
5. The repository starts at architecture_only with empty capability and claim inventories and stays there until a measured run with its manifest and hashes exists. Implementation arrives as complete, tested modules; no placeholder logic or interface is committed ahead of it.
6. Licence: AGPL-3.0-or-later with a commercial licence available.

Alternatives considered

• Place the instrument inside SC-NeuroCore. Rejected: the instrument is application-neutral and measures control loops that have nothing to do with neuromorphic computing; coupling it to one library would also couple its licence and release cycle to that library.
• Use processor-side timing only (cycle counters or operating-system timestamps). Rejected: it shares clock, scheduler and interrupts with the system under measurement, which is the problem the instrument exists to avoid.
• Reuse an existing fabric latency circuit. Not possible as a whole: the published circuit measures one pair of signals, and no source release is stated in its publication. Its measurement principle is acknowledged as prior work.

Consequences

• SC-NeuroCore can obtain board-level latency and energy measurements of its peripherals through the COMPUTE profile without any of its code entering this repository.
• The manifest format and slot interface become a versioned public contract once published; breaking changes need a new schema identifier and a new decision record.
• Results carry the limits of one board type and its power-monitor rail layout.