Module emit_sv 

SystemVerilog emitter for SC IR graphs.

Produces synthesizable RTL that instantiates modules from hdl/.

Generated module interface:

• Clock: clk
• Reset: rst_n (active-low)
• One port per sc.input / sc.output operation
• Internal wiring for all intermediate values

Constants

ATTN_DATA_WIDTH 🔒

ATTN_FRACTION 🔒

GRAPH_DATA_WIDTH 🔒

GRAPH_FRACTION 🔒

KURAMOTO_DATA_WIDTH 🔒

KURAMOTO_FRACTION 🔒

KURAMOTO_LUT_SIZE 🔒

Functions

attn_fixed 🔒

Quantise a real value into the signed Q8.16 attention datapath, rejecting out-of-range constants.

const_f64_vec 🔒

Resolve a constant vector operand to its f64 values, if present.

emit

Emit a synthesizable SystemVerilog module from an SC graph.

emit_concat_u32 🔒

emit_constant 🔒

emit_dense_fold_plan_comment 🔒

emit_graph_forward 🔒

Instantiate the fixed-point sc_graph_forward core for a single graph aggregation.

emit_kuramoto_step 🔒

Instantiate the fixed-point sc_kuramoto_step core for a single Kuramoto IR step.

emit_ram_style_attribute 🔒

emit_softmax_attention 🔒

Instantiate the fixed-point sc_softmax_attention core for a single attention op.

emit_systemverilog_with_target

Emit a synthesizable SystemVerilog module and a resource estimate for a target.

emit_target_dsp_attribute 🔒

find_value_width 🔒

graph_fixed 🔒

Quantise a real value into the signed Q8.16 graph datapath, rejecting out-of-range constants.

kuramoto_fixed 🔒

Quantise a real value into the signed Q8.16 Kuramoto datapath, rejecting out-of-range constants.

kuramoto_half_phase_modulus 🔒

Q(FRACTION) representation of the pi half-phase modulus.

kuramoto_osc_count 🔒

Infer the oscillator count from the phase operand’s vector length.

kuramoto_phase_modulus 🔒

Q(FRACTION) representation of the 2*pi phase modulus.

pack_q_bus 🔒

Pack signed Q(FRACTION) words of width bits into a Verilog concatenation with element 0 at the LSB.

q_fixed 🔒

Quantise a finite real into signed Q(frac) of width bits, or None when the value is non-finite or falls outside the representable two’s-complement range.

signed_q_literal 🔒

Format a signed fixed-point value as a Verilog literal (sign outside the sized base).

softmax_attention_shape 🔒

Infer the (q_rows, k_rows, v_cols) attention shape from the constant operand lengths and dim_k, or None when the operands are non-constant or ill-shaped.

type_to_width 🔒

value_to_wire 🔒