Module emit_sv 

SystemVerilog emitter for SC IR graphs.

Produces synthesizable RTL that instantiates modules from hdl/.

Generated module interface:

• Clock: clk
• Reset: rst_n (active-low)
• One port per sc.input / sc.output operation
• Internal wiring for all intermediate values

Functions

emit

Emit a synthesizable SystemVerilog module from an SC graph.

emit_concat_u32 🔒

emit_constant 🔒

emit_dense_fold_plan_comment 🔒

emit_ram_style_attribute 🔒

emit_systemverilog_with_target

Emit a synthesizable SystemVerilog module and a resource estimate for a target.

emit_target_dsp_attribute 🔒

find_value_width 🔒

type_to_width 🔒

value_to_wire 🔒