Enum SvTarget 

pub enum SvTarget {
    Generic,
    Zynq7 {
        device: String,
        clock_mhz: u32,
    },
    ZynqUltraScalePlus {
        sku: SkuKind,
        clock_mhz: u32,
        dsp_budget: u32,
        bram_36k_budget: u32,
        uram_budget: u32,
        prefer_uram_over_bram_above_bits: u64,
    },
}

SystemVerilog emission target.

Variants

Generic

Zynq7

Fields

device: String

clock_mhz: u32

ZynqUltraScalePlus

Fields

sku: SkuKind

clock_mhz: u32

dsp_budget: u32

bram_36k_budget: u32

uram_budget: u32

prefer_uram_over_bram_above_bits: u64

Implementations

impl SvTarget

pub fn zynq_ultrascale_plus(sku: SkuKind, clock_mhz: u32) -> Self

pub fn target_name(&self) -> String

pub fn clock_mhz(&self) -> u32

pub fn device_part(&self) -> String

pub fn dsp_primitive(&self) -> &'static str

pub fn dsp_attribute(&self) -> Option<&'static str>

pub fn ram_style_for_bits(&self, bits: u64) -> Option<&'static str>

pub fn dense_fold_plan( &self, n_inputs: usize, n_outputs: usize, ) -> Option<DenseFoldPlan>

pub fn header_comment(&self) -> String

pub fn estimate_graph(&self, graph: &ScGraph) -> ResourceReport

Trait Implementations

impl Clone for SvTarget

fn clone(&self) -> SvTarget

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SvTarget

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for SvTarget

impl PartialEq for SvTarget

fn eq(&self, other: &SvTarget) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for SvTarget