NIR Bridge API¶
sc_neurocore.nir_bridge
¶
NIR integration for SC-NeuroCore.
Provides bidirectional conversion between NIR graphs and SC-NeuroCore networks.
>>> import nir
>>> from sc_neurocore.nir_bridge import from_nir
>>> graph = nir.read("model.nir")
>>> network = from_nir(graph, dt=1.0)
>>> network.run(inputs, steps=100)
HardwareNoiseAnnotation
dataclass
¶
Measured target noise that can be replayed in simulation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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to_dict()
¶
Return a JSON-serialisable noise annotation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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NeuromorphicHardwareProfile
dataclass
¶
NIR extension profile for a named neuromorphic target.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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to_manifest()
¶
Return the profile in deterministic manifest form.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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SCMappingConstraints
dataclass
¶
SC-specific constraints used before lowering NIR graphs to a target.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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to_dict()
¶
Return a JSON-serialisable representation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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SiliconMappingConfig
dataclass
¶
Configuration for NIR silicon mapping report generation.
Source code in src/sc_neurocore/nir_bridge/silicon_mapping.py
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NeuromorphicAdapterPackage
dataclass
¶
Deterministic handoff package for one neuromorphic hardware target.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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manifest()
¶
Return a JSON-serialisable adapter manifest.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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files()
¶
Return deterministic package files keyed by relative path.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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ConnectionSpec
dataclass
¶
Weighted edge between two neuron populations.
Attributes¶
src : str
Source population name.
dst : str
Destination population name.
weights : np.ndarray[Any, Any]
Weight matrix of shape (n_dst, n_src) in float32.
Row i contains the weights from all source neurons to
destination neuron i.
bias : np.ndarray[Any, Any] | None
Optional bias vector of shape (n_dst,).
delay_steps : int | tuple[int, ...]
Number of explicit unit-delay timesteps on this connection. A scalar
applies to all source columns; a tuple carries one delay per source
column for heterogeneous NIR Delay vectors.
source_threshold : np.ndarray[Any, Any] | None
Optional threshold vector applied to source signals before the weight
matrix. Represents NIR Threshold on the source side.
destination_threshold : np.ndarray[Any, Any] | None
Optional threshold vector applied after this connection's affine
accumulation and before the destination population input.
Source code in src/sc_neurocore/nir_bridge/neuron_graph.py
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NeuronGraph
dataclass
¶
Complete network description ready for FPGA compilation.
Attributes¶
populations : list[NeuronSpec] Ordered list of neuron populations (topological order). connections : list[ConnectionSpec] Weighted connections between populations. input_pop : str Name of the input population. output_pop : str Name of the output population. dt : float Global simulation timestep. hierarchy : tuple[HierarchyInstanceSpec, ...] Nested NIR graph instances that were inlined for flat hardware lowering but must remain visible in SC-NIR hierarchy metadata.
Source code in src/sc_neurocore/nir_bridge/neuron_graph.py
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total_neurons
property
¶
Total neuron count across all populations.
total_synapses
property
¶
Total synapse count across all connections.
neuron_types
property
¶
Set of unique neuron types in the graph.
summary()
¶
Human-readable summary of the network graph.
Source code in src/sc_neurocore/nir_bridge/neuron_graph.py
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NeuronSpec
dataclass
¶
One neuron population (layer) in the compiled graph.
Attributes¶
name : str
Unique population identifier (matches the NIR node name).
neuron_type : str
Canonical neuron type: "lif", "if", "li",
"cuba_lif", "cuba_li".
n_neurons : int
Number of neurons in this population.
params : dict[str, np.ndarray[Any, Any]]
Neuron parameters keyed by canonical names:
tau, r, v_leak, v_threshold, v_reset,
tau_syn, tau_mem, w_in (type-dependent).
dt : float
Simulation timestep used during NIR import.
Source code in src/sc_neurocore/nir_bridge/neuron_graph.py
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QuantisedGraph
dataclass
¶
NeuronGraph with all parameters converted to Q-format integers.
Attributes¶
populations : list[NeuronSpec] Populations with integer-valued parameters (Q-encoded). connections : list[ConnectionSpec] Connections with integer-valued weight matrices (Q-encoded). q : Q88 The fixed-point format configuration used. input_pop : str Input population name. output_pop : str Output population name. dt : float Global timestep. warnings : list[str] Overflow/underflow warnings generated during quantisation. total_neurons : int Total neuron count. total_synapses : int Total synapse count.
Source code in src/sc_neurocore/nir_bridge/quantise_params.py
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NetworkCompilationResult
dataclass
¶
All artefacts from a network-level FPGA compilation.
Attributes¶
neuron_modules : dict[str, str]
Mapping from neuron type to Verilog source.
weight_rom : str
Weight ROM Verilog source.
top_module : str
Top-level interconnect Verilog source.
module_name : str
Top-level module name.
total_neurons : int
Total neuron count.
total_synapses : int
Total synapse count.
q_format : str
Q-format label (e.g. "Q8.8").
interconnect : str
"direct" or "aer".
warnings : list[str]
Quantisation and compilation warnings.
scnir_document : SCNIRDocument
SC-aware metadata document consumed by the compilation artefacts.
scnir_source_modules : dict[str, str]
Concrete stochastic source HDL modules keyed by Verilog module name.
scnir_source_manifest : tuple[SCNIRHDLSourceManifestEntry, ...]
Deterministic manifest mapping SC-NIR streams to source modules.
scnir_external_inputs : tuple[SCNIRExternalInputManifestEntry, ...]
Deterministic flattened input-bus layout for external source names.
scnir_hierarchy_modules : dict[str, str]
Standalone SC-NIR hierarchy boundary modules keyed by module name.
Source code in src/sc_neurocore/nir_bridge/fpga_compiler.py
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available_hardware_profiles()
¶
Return all known hardware profiles in deterministic order.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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build_nir_hardware_manifest(targets=None)
¶
Build a deterministic manifest for NIR hardware-extension planning.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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build_noise_annotation(target_id, observations)
¶
Validate measured hardware noise and prepare it for simulation replay.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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get_hardware_profile(target_id)
¶
Return one hardware profile by identifier.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
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build_silicon_mapping_report(source, config=None)
¶
Build a deterministic target-mapping report for a parsed NIR network.
Source code in src/sc_neurocore/nir_bridge/silicon_mapping.py
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write_silicon_mapping_report(output_dir, source, config=None)
¶
Write nir_silicon_mapping_report.json in deterministic form.
Source code in src/sc_neurocore/nir_bridge/silicon_mapping.py
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build_neuromorphic_adapter_bundle(source, targets=SUPPORTED_ADAPTER_TARGETS, config=None)
¶
Build deterministic adapter packages for multiple targets.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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build_neuromorphic_adapter_package(source, target_id, config=None)
¶
Build one Loihi 2 or SpiNNaker2 adapter handoff package.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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write_neuromorphic_adapter_bundle(output_dir, source, targets=SUPPORTED_ADAPTER_TARGETS, config=None)
¶
Write Loihi 2/SpiNNaker2 adapter manifests and reports to disk.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
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from_scnetwork(network, dt=None)
¶
Convert a parsed SCNetwork to a NeuronGraph for FPGA compilation.
Walks the topologically-sorted node list and partitions nodes into neuron populations and weighted connections. Pass-through nodes (Input, Output, Scale, Flatten, Threshold) are folded into the adjacent edges.
Parameters¶
network : SCNetwork
A parsed SC-NeuroCore network (from from_nir()).
dt : float, optional
Override the simulation timestep. If None, uses the
timestep stored in the network's neuron nodes.
Returns¶
NeuronGraph Network description ready for FPGA compilation.
Raises¶
ValueError If the network contains no neuron populations or no connections.
Source code in src/sc_neurocore/nir_bridge/neuron_graph.py
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quantise_graph(graph, q)
¶
Convert all floating-point parameters to Q-format integers.
Parameters¶
graph : NeuronGraph Network with float32 parameters. q : Q88 Target fixed-point format.
Returns¶
QuantisedGraph Network with integer-valued parameters and quantisation warnings.
Source code in src/sc_neurocore/nir_bridge/quantise_params.py
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compile_network_to_fpga(graph, *, module_name='sc_nir_network', data_width=16, fraction=8, bitstream_length=256, source_kind='lfsr', base_seed=1, target='artix7', online_learning=None)
¶
Compile a NeuronGraph to synthesisable Verilog RTL.
End-to-end pipeline:
- Quantise all parameters to the target Q-format.
- Generate one Verilog module per unique neuron type.
- Generate a combined weight ROM.
- Generate a top-level interconnect module (direct or AER).
Parameters¶
graph : NeuronGraph
Network description (from from_scnetwork()).
module_name : str
Top-level Verilog module name.
data_width : int
Fixed-point total width (16 for Q8.8, 32 for Q16.16).
fraction : int
Fractional bits.
bitstream_length : int
SC-NIR bitstream length metadata propagated into compilation artefacts.
source_kind : {"lfsr", "sobol"}
Hardware stochastic source family materialised from SC-NIR metadata.
base_seed : int
First deterministic source seed; stream index increments from this base.
target : str
FPGA target for resource estimation hints.
online_learning : Mapping[str, Mapping[str, Any]] | None
Optional validated per-weight-stream SC-NIR online-learning annotations,
keyed by deterministic stream id such as "conn.src_to_dst.weight".
Returns¶
NetworkCompilationResult All generated Verilog sources and compilation metadata.
Raises¶
ValueError If the graph is empty or contains unsupported neuron types.
Source code in src/sc_neurocore/nir_bridge/fpga_compiler.py
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from_nir(source, dt=1.0, reset_mode='reset')
¶
Convert a NIR graph/source to an SC-NeuroCore network.
Source code in src/sc_neurocore/nir_bridge/__init__.py
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to_nir(network, path=None)
¶
Export an SC-NeuroCore network to NIR.
Source code in src/sc_neurocore/nir_bridge/__init__.py
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Parser¶
sc_neurocore.nir_bridge.parser
¶
SCNetwork
dataclass
¶
Executable network parsed from a NIR graph.
Nodes are stored by name. Edges define the forward pass order.
Calling run() feeds input through the graph for the given
number of timesteps and returns the output node's accumulated result.
Recurrent edges (cycles) are automatically handled by inserting unit-delay nodes that feed from the previous timestep.
Source code in src/sc_neurocore/nir_bridge/parser.py
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from_nir(source, dt=1.0, reset_mode='reset')
classmethod
¶
Build an SCNetwork directly from a NIR graph or file path.
Source code in src/sc_neurocore/nir_bridge/parser.py
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to_hardware(*, module_name='sc_nir_network', data_width=16, fraction=8, bitstream_length=256, source_kind='lfsr', base_seed=1, target='artix7', dt=None, online_learning=None)
¶
Compile this parsed network to the existing FPGA artefact bundle.
Source code in src/sc_neurocore/nir_bridge/parser.py
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step(inputs)
¶
Execute one timestep through the graph.
Parameters¶
inputs : dict mapping input node name → input array
Returns¶
dict mapping output node name → output array
Source code in src/sc_neurocore/nir_bridge/parser.py
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run(inputs, steps=100)
¶
Run the network for multiple timesteps.
Parameters¶
inputs : dict mapping input node name → input array (constant across steps) steps : number of timesteps
Returns¶
dict mapping output node name → list of output arrays per timestep
Source code in src/sc_neurocore/nir_bridge/parser.py
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reset()
¶
Reset all stateful nodes.
Source code in src/sc_neurocore/nir_bridge/parser.py
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summary()
¶
Human-readable network summary.
Source code in src/sc_neurocore/nir_bridge/parser.py
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SCSubgraphNode
dataclass
¶
Executable wrapper for a nested NIR subgraph (single I/O port).
Source code in src/sc_neurocore/nir_bridge/parser.py
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SCMultiPortSubgraphNode
dataclass
¶
Executable wrapper for a nested NIR subgraph with multiple I/O ports.
Supports modular architectures where subgraphs expose multiple named inputs and outputs (e.g., encoder-decoder, skip connections).
Source code in src/sc_neurocore/nir_bridge/parser.py
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forward(x)
¶
Single-input convenience: feeds x to first input, returns first output.
Source code in src/sc_neurocore/nir_bridge/parser.py
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forward_multi(inputs)
¶
Multi-port forward: provide named inputs, get named outputs.
Source code in src/sc_neurocore/nir_bridge/parser.py
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from_nir(source, dt=1.0, reset_mode='reset')
¶
Convert a NIR graph to an executable SC-NeuroCore network.
Parameters¶
source : nir.NIRGraph or str or Path NIR graph object, or path to a .nir file. dt : float Timestep for leaky integrator dynamics. reset_mode : str Spike reset mechanism: "reset" (v = v_reset, NIR spec default) or "subtract" (v = v - v_threshold, used by snnTorch).
Returns¶
SCNetwork Executable network with topologically sorted forward pass.
Source code in src/sc_neurocore/nir_bridge/parser.py
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Recurrent Edge Handling¶
Graphs with cycles (feedback connections) are automatically handled by
inserting unit-delay nodes on back edges. The delay node buffers the
previous timestep's value, breaking algebraic loops while preserving
temporal dynamics. See _UnitDelayNode.
Multi-Port Subgraphs¶
Nested NIR graphs with multiple inputs/outputs use SCMultiPortSubgraphNode,
which exposes forward_multi(inputs_dict) → outputs_dict for named I/O ports.
Import Boundary Validation¶
from_nir() accepts a nir.NIRGraph, string path, or Path. File reads are
wrapped as ValueError on malformed or unreadable NIR payloads. Parsed graphs
must expose mapping-like nodes and sequence-like edges, all node names and edge
endpoints must be non-empty strings, and every edge endpoint must reference an
existing node before the graph is lowered.
High-Level Hardware Path¶
SCNNetwork is the public alias for the parsed NIR SCNetwork. It supports
SCNNetwork.from_nir(...) for import and network.to_hardware(...) for
lowering through the same from_scnetwork() and compile_network_to_fpga()
pipeline used by the lower-level compiler API.
Node Map¶
sc_neurocore.nir_bridge.node_map
¶
NODE_MAP = {nir.Input: lambda name, node, **kw: SCInputNode(name=name, shape=(tuple((int(x)) for x in (next(iter(node.input_type.values())).flatten())) if node.input_type else ())), nir.Output: lambda name, node, **kw: SCOutputNode(name=name, shape=(tuple((int(x)) for x in (next(iter(node.output_type.values())).flatten())) if node.output_type else ())), nir.LIF: lambda name, node, **kw: SCLIFNode.from_nir(name, node, dt=(kw.get('dt', 1.0)), reset_mode=(kw.get('reset_mode', 'reset'))), nir.IF: lambda name, node, **kw: SCIFNode.from_nir(name, node, dt=(kw.get('dt', 1.0)), reset_mode=(kw.get('reset_mode', 'reset'))), nir.LI: lambda name, node, **kw: SCLINode.from_nir(name, node, dt=(kw.get('dt', 1.0))), nir.I: lambda name, node, **kw: SCIntegratorNode.from_nir(name, node, dt=(kw.get('dt', 1.0))), nir.Affine: lambda name, node, **kw: SCAffineNode.from_nir(name, node), nir.Linear: lambda name, node, **kw: SCLinearNode.from_nir(name, node), nir.Scale: lambda name, node, **kw: SCScaleNode.from_nir(name, node), nir.Threshold: lambda name, node, **kw: SCThresholdNode.from_nir(name, node), nir.Flatten: lambda name, node, **kw: SCFlattenNode.from_nir(name, node), nir.Delay: lambda name, node, **kw: SCDelayNode.from_nir(name, node, dt=(kw.get('dt', 1.0))), nir.CubaLIF: lambda name, node, **kw: SCCubaLIFNode.from_nir(name, node, dt=(kw.get('dt', 1.0)), reset_mode=(kw.get('reset_mode', 'reset'))), nir.CubaLI: lambda name, node, **kw: SCCubaLINode.from_nir(name, node, dt=(kw.get('dt', 1.0))), nir.SumPool2d: lambda name, node, **kw: SCSumPool2dNode.from_nir(name, node), nir.AvgPool2d: lambda name, node, **kw: SCAvgPool2dNode.from_nir(name, node), nir.Conv1d: lambda name, node, **kw: SCConv1dNode.from_nir(name, node), nir.Conv2d: lambda name, node, **kw: SCConv2dNode.from_nir(name, node)}
module-attribute
¶
SCLIFNode
dataclass
¶
LIF neuron mapped from NIR LIF primitive.
NIR LIF: taudv/dt = (v_leak - v) + RI, spike when v > v_threshold Euler: v += ((v_leak - v) + R*I) * dt/tau
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCIFNode
dataclass
¶
IF neuron — integrator with threshold, no leak.
NIR IF: dv/dt = RI, spike when v > v_threshold Euler: v += RI*dt
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCLINode
dataclass
¶
Leaky integrator — LIF without threshold.
NIR LI: taudv/dt = (v_leak - v) + RI
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCIntegratorNode
dataclass
¶
Pure integrator: dv/dt = RI (no leak, no threshold). Euler: v += RI*dt
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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n_neurons
property
¶
Number of integrator state channels.
SCAffineNode
dataclass
¶
Dense linear transform with bias: y = Wx + b
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCLinearNode
dataclass
¶
Matrix multiply without bias: y = Wx
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCScaleNode
dataclass
¶
Element-wise scaling: y = s * x
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCThresholdNode
dataclass
¶
Spike threshold: y = 1 if x > threshold else 0
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCFlattenNode
dataclass
¶
Reshape tensor — flatten dimensions.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCInputNode
dataclass
¶
Graph entry point — passes input through unchanged.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCOutputNode
dataclass
¶
Graph exit point — collects output.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCDelayNode
dataclass
¶
Temporal delay: output = input(t - delay).
NIR Delay: I(t - tau). Implemented as a circular buffer per element. Delay values are rounded to integer timesteps.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCCubaLIFNode
dataclass
¶
Current-based LIF with synaptic filter.
tau_syn * dI_syn/dt = -I_syn + w_in * I
tau_mem * dv/dt = (v_leak - v) + R * I_syn spike when v > v_threshold, reset to v_reset
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCCubaLINode
dataclass
¶
Current-based leaky integrator (CubaLIF without threshold).
tau_syn * dI_syn/dt = -I_syn + w_in * I
tau_mem * dv/dt = (v_leak - v) + R * I_syn
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCConv1dNode
dataclass
¶
1D convolution: y = conv1d(x, weight) + bias.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCConv2dNode
dataclass
¶
2D convolution: y = conv2d(x, weight) + bias.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCSumPool2dNode
dataclass
¶
2D sum pooling: sum over spatial kernel windows.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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SCAvgPool2dNode
dataclass
¶
2D average pooling: SumPool / kernel_area.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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map_node(name, node, **kwargs)
¶
Convert a single NIR node to its SC-NeuroCore equivalent.
Source code in src/sc_neurocore/nir_bridge/node_map.py
| Python | |
|---|---|
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Export¶
sc_neurocore.nir_bridge.export
¶
to_nir(network, path=None)
¶
Export an SC-NeuroCore SCNetwork to NIR format.
Parameters¶
network : SCNetwork The network to export. path : str or Path, optional If provided, write the NIR graph to this file.
Returns¶
nir.NIRGraph
Source code in src/sc_neurocore/nir_bridge/export.py
| Python | |
|---|---|
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Hardware Target Manifests¶
sc_neurocore.nir_bridge.hardware_targets
¶
Capability manifests for NIR-to-neuromorphic-hardware planning.
SCMappingConstraints
dataclass
¶
SC-specific constraints used before lowering NIR graphs to a target.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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to_dict()
¶
Return a JSON-serialisable representation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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NeuromorphicHardwareProfile
dataclass
¶
NIR extension profile for a named neuromorphic target.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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to_manifest()
¶
Return the profile in deterministic manifest form.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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HardwareNoiseAnnotation
dataclass
¶
Measured target noise that can be replayed in simulation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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to_dict()
¶
Return a JSON-serialisable noise annotation.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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available_hardware_profiles()
¶
Return all known hardware profiles in deterministic order.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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get_hardware_profile(target_id)
¶
Return one hardware profile by identifier.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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build_nir_hardware_manifest(targets=None)
¶
Build a deterministic manifest for NIR hardware-extension planning.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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build_noise_annotation(target_id, observations)
¶
Validate measured hardware noise and prepare it for simulation replay.
Source code in src/sc_neurocore/nir_bridge/hardware_targets.py
| Python | |
|---|---|
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build_nir_hardware_manifest() records capability manifests for Akida,
Loihi 2, BrainScaleS-3, SpiNNaker2, and DYNAP-SE. These entries are planning
metadata, not live SDK integrations: each profile carries backend_status:
capability_manifest and only records NIR node support, SC bitstream ranges,
stream transport, stochastic sources, and noise channels that can be measured
and replayed in simulation.
from sc_neurocore.nir_bridge import build_nir_hardware_manifest, build_noise_annotation
manifest = build_nir_hardware_manifest(("loihi2", "spinnaker2", "akida"))
noise = build_noise_annotation("loihi2", {"spike_drop_rate": 0.001})
Noise annotations validate channel names and reject non-finite or negative measurements before they can influence simulation.
Loihi 2 / SpiNNaker2 Adapter Packages¶
sc_neurocore.nir_bridge.neuromorphic_adapters
¶
SDK-free adapter packages for Loihi 2 and SpiNNaker2 planning.
The functions in this module deliberately do not invoke Lava, SpiNNTools, or physical hardware. They create deterministic handoff artefacts from a NIR graph and the existing silicon-mapping report so downstream vendor-specific runs have an explicit manifest, fallback list, and hardware-noise contract.
NeuromorphicAdapterPackage
dataclass
¶
Deterministic handoff package for one neuromorphic hardware target.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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manifest()
¶
Return a JSON-serialisable adapter manifest.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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files()
¶
Return deterministic package files keyed by relative path.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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build_neuromorphic_adapter_package(source, target_id, config=None)
¶
Build one Loihi 2 or SpiNNaker2 adapter handoff package.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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build_neuromorphic_adapter_bundle(source, targets=SUPPORTED_ADAPTER_TARGETS, config=None)
¶
Build deterministic adapter packages for multiple targets.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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write_neuromorphic_adapter_bundle(output_dir, source, targets=SUPPORTED_ADAPTER_TARGETS, config=None)
¶
Write Loihi 2/SpiNNaker2 adapter manifests and reports to disk.
Source code in src/sc_neurocore/nir_bridge/neuromorphic_adapters.py
| Python | |
|---|---|
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build_neuromorphic_adapter_package() turns a parsed NIR graph into a
deterministic handoff package for either loihi2 or spinnaker2. The package
contains:
adapter_manifest.jsonwith lowering status, fallback requirements, selected bitstream length, and noise back-annotation hooks;nir_silicon_mapping_report.json, the full mapping report used to build the manifest;README.mddocumenting the vendor SDK boundary.
The adapter package is intentionally SDK-free. Loihi 2 execution still requires Lava/Loihi access, and SpiNNaker2 execution still requires the SpiNNaker2 SDK and board access. The package is therefore a reproducible planning and handoff artefact, not a hardware-execution claim.
from sc_neurocore.nir_bridge import write_neuromorphic_adapter_bundle
write_neuromorphic_adapter_bundle(
"build/neuromorphic_targets",
nir_graph,
targets=("loihi2", "spinnaker2"),
)