UVM Generator¶
The UVM generator turns a supported Verilog/SystemVerilog module header into a deterministic bundle of transaction, sequence, driver, monitor, scoreboard, coverage, agent, environment, top-level, assertion-bind, SymbiYosys, simulator-Makefile, and regression-list text.
The historical sc_neurocore.uvm_gen.uvm_gen module is a stable compatibility
facade. Focused private modules now own RTL parsing, configuration contracts,
generated-artifact packaging, UVM component emission, simulator/formal harness
emission, and orchestration. The package-level 13-name export set, callable
signatures, class identities, pickle-qualified paths, and representative
generated bytes remain compatible with the pre-split implementation.
The focused UVM cohort contains 82 tests. All 422 statements and 112 branches across the eight governed package modules are covered, including six pinned parent-payload SHA-256 values for default and configured LIF, dense, and port-less inputs. Strict typing and NumPy-docstring policy cover the complete split surface.
Draft verification-IP surface
The repository architecture map continues to classify uvm_gen as a draft
stub surface. This modularisation proves Python API and deterministic-text
compatibility; it does not claim that every emitted bundle compiles under
a vendor UVM installation or that the generated SymbiYosys harness is
promotion-ready. The auto-generated Go, Rust, Julia, and Mojo placeholder
mirrors are not wired runtime counterparts and remain separate backlog
debt. No cross-language or throughput claim applies to this static text
generator.
Quick Start¶
from sc_neurocore.uvm_gen import (
UVMGenerator, RTLModule, StimulusConfig, CoverageSpec,
)
sc_neurocore.uvm_gen.uvm_gen
¶
Expose the stable UVM generator API over focused responsibility modules.
RTL parsing, configuration, generated-artifact contracts, UVM component emission, simulator/formal harness emission, and orchestration live in private modules. Historical imports and pickle-qualified names remain stable here.